From: Keir Fraser Date: Tue, 13 May 2008 09:40:49 +0000 (+0100) Subject: Intel vmx: To correctly detect default1 vmx features which may X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~14215^2~15 X-Git-Url: https://dgit.raspbian.org/%22http:/www.example.com/cgi/%22https://%22%22/%22http:/www.example.com/cgi/%22https:/%22%22?a=commitdiff_plain;h=0c4432e7b53dfc11397dd98e6635e2261296ec05;p=xen.git Intel vmx: To correctly detect default1 vmx features which may actually be switched to 0, we must check VMX_BASIC_MSR[55] and possibly check a set of 'true' feature MSRs. Signed-off-by: Jun Nakajima Signed-off-by: Keir Fraser --- diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index ab8b2d9b89..97e65c54a3 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -72,13 +72,15 @@ static u32 adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, u32 msr) static void vmx_init_vmcs_config(void) { - u32 vmx_msr_low, vmx_msr_high, min, opt; + u32 vmx_basic_msr_low, vmx_basic_msr_high, min, opt; u32 _vmx_pin_based_exec_control; u32 _vmx_cpu_based_exec_control; u32 _vmx_secondary_exec_control = 0; u32 _vmx_vmexit_control; u32 _vmx_vmentry_control; + rdmsr(MSR_IA32_VMX_BASIC, vmx_basic_msr_low, vmx_basic_msr_high); + min = (PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING); opt = PIN_BASED_VIRTUAL_NMIS; @@ -122,9 +124,14 @@ static void vmx_init_vmcs_config(void) if ( _vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT ) { - /* To use EPT we expect to be able to clear certain intercepts. */ - uint32_t must_be_one, must_be_zero; - rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, must_be_one, must_be_zero); + /* + * To use EPT we expect to be able to clear certain intercepts. + * We check VMX_BASIC_MSR[55] to correctly handle default1 controls. + */ + uint32_t must_be_one, must_be_zero, msr = MSR_IA32_VMX_PROCBASED_CTLS; + if ( vmx_basic_msr_high & (1u << 23) ) + msr = MSR_IA32_VMX_TRUE_PROCBASED_CTLS; + rdmsr(msr, must_be_one, must_be_zero); if ( must_be_one & (CPU_BASED_INVLPG_EXITING | CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING) ) @@ -150,41 +157,40 @@ static void vmx_init_vmcs_config(void) _vmx_vmentry_control = adjust_vmx_controls( min, opt, MSR_IA32_VMX_ENTRY_CTLS); - rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); - if ( !vmx_pin_based_exec_control ) { /* First time through. */ - vmcs_revision_id = vmx_msr_low; + vmcs_revision_id = vmx_basic_msr_low; vmx_pin_based_exec_control = _vmx_pin_based_exec_control; vmx_cpu_based_exec_control = _vmx_cpu_based_exec_control; vmx_secondary_exec_control = _vmx_secondary_exec_control; vmx_vmexit_control = _vmx_vmexit_control; vmx_vmentry_control = _vmx_vmentry_control; - cpu_has_vmx_ins_outs_instr_info = !!(vmx_msr_high & (1U<<22)); + cpu_has_vmx_ins_outs_instr_info = !!(vmx_basic_msr_high & (1U<<22)); } else { /* Globals are already initialised: re-check them. */ - BUG_ON(vmcs_revision_id != vmx_msr_low); + BUG_ON(vmcs_revision_id != vmx_basic_msr_low); BUG_ON(vmx_pin_based_exec_control != _vmx_pin_based_exec_control); BUG_ON(vmx_cpu_based_exec_control != _vmx_cpu_based_exec_control); BUG_ON(vmx_secondary_exec_control != _vmx_secondary_exec_control); BUG_ON(vmx_vmexit_control != _vmx_vmexit_control); BUG_ON(vmx_vmentry_control != _vmx_vmentry_control); - BUG_ON(cpu_has_vmx_ins_outs_instr_info != !!(vmx_msr_high & (1U<<22))); + BUG_ON(cpu_has_vmx_ins_outs_instr_info != + !!(vmx_basic_msr_high & (1U<<22))); } /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ - BUG_ON((vmx_msr_high & 0x1fff) > PAGE_SIZE); + BUG_ON((vmx_basic_msr_high & 0x1fff) > PAGE_SIZE); #ifdef __x86_64__ /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ - BUG_ON(vmx_msr_high & (1u<<16)); + BUG_ON(vmx_basic_msr_high & (1u<<16)); #endif /* Require Write-Back (WB) memory type for VMCS accesses. */ - BUG_ON(((vmx_msr_high >> 18) & 15) != 6); + BUG_ON(((vmx_basic_msr_high >> 18) & 15) != 6); } static struct vmcs_struct *vmx_alloc_vmcs(void) diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 71f803fe36..69221ced3f 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -135,6 +135,10 @@ #define MSR_IA32_VMX_CR4_FIXED0 0x488 #define MSR_IA32_VMX_CR4_FIXED1 0x489 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b +#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e +#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f +#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 #define IA32_FEATURE_CONTROL_MSR 0x3a #define IA32_FEATURE_CONTROL_MSR_LOCK 0x0001 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX 0x0002